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Freescale Semiconductor Data Sheet: Product Preview
Document Number: MSC8144 Rev. 1, 5/2007
MSC8144
FC-PBGA-783 29 mm x 29 mm
Quad Core Digital Signal Processor
* Four StarCoreTM SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes. * Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets. * 128 Kbyte L2 shared instruction cache. * 512 Kbyte M2 memory for critical data and temporary data buffering. * 10 Mbyte 128-b8t wide M3 memory. * 96 Kbyte boot ROM. * Three input clocks (shared, global, and differential). * Four PLLs (system, core, global, and serial RapidIO). * DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2. * DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration. * Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. * QUICC EngineTM technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three communication controllers with one ATM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores. - The two Ethernet controllers support 10/100/1000 Mbps operations via MII/RMII/SMII/RGMII/SGMII and the SGMII protocol using a 4-pin SerDes interface at 1000 Mbps data rate only. - The ATM controller supports UTOPIA level II 8/16 bits at 25/50 MHz in UTOPIA/POS mode with adaptation layer support AAL0, AAL2, and AAL5. PCI designed to comply with the PCI specification revision 2.2 at 33 MHz or 66 MHz with access to all PCI address spaces. Serial RapidIO(R) 1x/4x endpoint corresponds to Specification 1.2 of the RapidIO trade association, and supports read, write, messages, doorbells, and maintenance accesses in inbound mode, and messages and doorbells in outbound mode. I/O interrupt concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to INT_OUT, NMI_OUT, and the cores. UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. Serial peripheral interface (SPI). Four timer modules, each with four configurable16-bit timers. Four software watchdog timer (SWT) modules. Up to 32 general-purpose input/output (GPIO) ports, 16 of which can be configured as maskable interrupt inputs. I2C interface that allows booting from EEPROM devices. Eight programmable hardware semaphores. Thirty two virtual maskable interrupts and one virtual NMI that can be generated by a simple write access. Optional booting via serial RapidIO port, PCI, I2C, SPI, or Ethernet interfaces.
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Note:
This document supports mask set M31H.
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2007. All rights reserved.
Table of Contents
1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27 2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .27 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29 2.7 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .65 3.1 Start-up Sequencing Recommendations . . . . . . . . . . .65 3.2 Power Supply Design Considerations. . . . . . . . . . . . . .66 3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66 3.4 External DDR SDRAM Selection . . . . . . . . . . . . . . . . .75 3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .76 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Figure 13.Transmitter Output Compliance Mask . . . . . . . . . . . . . . Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17.PCI Input AC Timing Measurement Conditions . . . . . . . Figure 18.PCI Output AC Timing Measurement Condition . . . . . . Figure 19.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25.MII Management Interface Timing . . . . . . . . . . . . . . . . . Figure 26.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . Figure 30.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . Figure 33.UTOPIA AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34.UTOPIA AC Timing (External Clock) . . . . . . . . . . . . . . . Figure 35.UTOPIA AC Timing (Internal Clock) . . . . . . . . . . . . . . . Figure 36.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37.SPI AC Timing in Slave Mode (External Clock). . . . . . . Figure 38.SPI AC Timing in Master Mode (Internal Clock) . . . . . . Figure 39.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . Figure 42.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . Figure 43.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . Figure 44.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 45.VDDM3, VDDM3IO and V25M3 Power-on Sequence . . . . . Figure 47.MSC8144 Mechanical Information, 783-ball FC-PBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 48 49 51 51 51 52 53 53 53 54 55 55 56 56 57 57 58 59 60 60 60 61 61 62 62 63 63 64 64 64 65 77
3
4 5 6 7
List of Figures
MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 StarCore SC3400 DSP Core Subsystem Block Diagram 3 MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4 MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5 SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31 Overshoot/Undershoot Voltage for VIH and VIL. . . . . . . 35 Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 8. Timing for a Reset Configuration Write . . . . . . . . . . . . . 39 Figure 9. Timing for tDDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41 Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12.Differential VPP of Transmitter or Receiver . . . . . . . . . . 43 Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 2 Freescale Semiconductor
DDR Interface 16/32-bit at 400 MHz data rate 512 Kbytes M2 Memory 10 Mbytes M3 Memory 128-bit at 400 MHz CLASS QUICC Engine Subsystem DDR Controller
I/O-Interrupt Concentrator
UART Clocks Timers Reset
Four DSP Subsystems
128 Kbyte L2 ICache
Dual RISC Processors Ethernet Ethernet ATM SPI
Serial RapidIO Subsystem
Semaphores Virtual Interrupts Boot ROM I2C Other Modules
8 TDMs
DMA
PCI
RMU
SRIO
JTAG Eight TDMs 256-Channels each 10/100/1000 Mbps 10/100/1000 Mbps
SPI
PCI 32-bit 33/66 MHz 1x/4x
Note: The arrow direction indicates master or slave.
16-bit/8-bit UTOPIA
Figure 1. MSC8144 Block Diagram
Two Internal Buses (128 bits wide each)
Interrupts
Bus Interface IQBus TWB DQBus
EPIC
Timer
Task Protection Debug Support OCE30 DPU Instruction Cache
WriteThrough Buffer
Data Cache
WriteBack Buffer
Address Translation MMU
(WTB)
(WBB)
SC3400 Core
P-bus Xa-bus Xb-bus
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 3
Pin Assignments and Reset States
1
Pin Assignments and Reset States
This section includes diagrams of the MSC8144 package ball grid array layouts and tables showing how the pinouts are allocated for the package.
1.1
FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
Top View
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 19 20 21 22 23 24 25 26 27 28
MSC8144
Figure 3. MSC8144 FC-PBGA Package, Top View
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 4 Freescale Semiconductor
Bottom View
AH AG AF AE AD AC AB AA Y W V U
R P N M L K J H G F E D C B A 1 2 3 4 5 6
Figure 4. MSC8144 FC-PBGA Package, Bottom View
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 5
MSC8144
7 8 9 10 11 12 13 15 14 16 17 18 19 20 21 22 23 24 25 26 27 28
T
1.2
Signal List By Ball Location
Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The specified reference supply must be tied to the voltage level specified in this document if any of the related signal functions are used (active). Table 1. Signal List by Ball Number
Ball Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 B1 B2 B3 B4 B5 B6 B7 B8 B9 GND GE2_RX_ER/PCI_AD31 VDDGE2 GE2_RX_DV/PCI_AD30 GE2_TD0/PCI_CBE0 SRIO_IMP_CAL_RX Reserved1 Reserved
1
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND Ethernet 2 PCI Ethernet 2 VDDGE2 VDDGE2 Ethernet 2 Ethernet 2 PCI PCI Ethernet 2 Ethernet 2 VDDGE2 VDDGE2 VDDSXC -- -- -- -- VDDSXC VDDSXC VDDSXC VDDSXC VDDSXC GNDRIOPLL GNDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC VDDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC VDDSXC VDDSXP VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- Ethernet 2 Ethernet 2 PCI PCI Ethernet Ethernet 2 Ethernet 2 VDDGE2 VDDGE2 VDDGE2 GND Ethernet VDDGE2 GNDSXC -- --
Reserved1 Reserved1 SRIO_RXD0 VDDSXC SRIO_RXD1 VDDSXC SRIO_REF_CLK VDDRIOPLL GNDSXC SRIO_RXD2/ GE1_SGMII_RX VDDSXC SRIO_RXD3/ GE2_SGMII_RX VDDSXC SRIO_IMP_CAL_TX MDQ28 MDQ29 MDQ30 MDQ31 MDQS3 Reserved1 GE2_TD1/PCI_CBE1 GE2_TX_EN/PCI_CBE2 GE_MDIO GND GE_MDC GNDSXC Reserved1 Reserved
1
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 6 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply -- -- VDDSXC GNDSXC VDDSXC GNDSXC VDDSXC -- VDDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC GNDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC GNDSXC GNDSXP VDDDDR VDDDDR GND VDDDDR VDDDDR -- Ethernet 2 PCI Ethernet 2 VDDGE2 VDDGE2 TDM TDM PCI PCI Ethernet 2 Ethernet 2 UTOPIA UTOPIA VDDGE2 VDDGE2 VDDGE2 Ethernet 2 PCI Ethernet 2 VDDGE2 -- -- -- -- VDDSXP VDDSXP VDDSXP VDDSXP GNDSXC GNDRIOPLL -- VDDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP
Signal Name
Reserved1 Reserved1 SRIO_RXD0 GNDSXC SRIO_RXD1 GNDSXC SRIO_REF_CLK Reserved1 VDDSXC SRIO_RXD2/ GE1_SGMII_RX GNDSXC SRIO_RXD3/ GE2_SGMII_RX GNDSXC GNDSXP MDQ27 VDDDDR GND VDDDDR MDQS3 Reserved1 GE2_RX_CLK/PCI_AD29 VDDGE2 TDM7RSYN/GE2_TD2/ PCI_AD2/UTP_TER TDM7RCLK/GE2_RD2/ PCI_AD0/UTP_RVL VDDGE2 GE2_RD0/PCI_AD27 Reserved1 Reserved
1
Reserved1 Reserved1 VDDSXP SRIO_TXD0 VDDSXP SRIO_TXD1 GNDSXC GNDRIOPLL Reserved1 VDDSXP SRIO_TXD2/GE1_SGMII_T X
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 7
Table 1. Signal List by Ball Number (continued)
Ball Number C21 C22 C23 C24 C25 C26 C27 C28 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 E1 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP VDDSXP VDDDDR VDDDDR VDDDDR GND VDDDDR -- Ethernet 2 PCI Ethernet 2 VDDGE2 GND TDM TDM UTOPIA TDM Ethernet 1 PCI PCI PCI PCI UTOPIA Ethernet 2 Ethernet 2 UTOPIA UTOPIA VDDGE2 VDDGE2 VDDGE1 VDDGE2 -- -- -- -- GNDSXP VDDSXP GNDSXP VDDSXP VDDSXC -- -- GNDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP GNDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP GNDSXP VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR --
Signal Name
VDDSXP SRIO_TXD3/GE2_SGMII_T X VDDSXP MDQ26 MDQ25 MDM3 GND MDQ24 Reserved1 GE2_RD1/PCI_AD28 GND TDM7TDAT/GE2_TD3/ PCI_AD3/UTP_TMD TDM7RDAT/GE2_RD3/ PCI_AD1/UTP_STA GE1_RD0/UTP_RD2/ PCI_CBE2 TDM7TCLK/GE2_TCK/ PCI_IDS/UTP_RER Reserved1 Reserved
1
Ethernet 1 UTOPIA Ethernet 2 UTOPIA
Reserved1 Reserved1 GNDSXP SRIO_TXD0 GNDSXP SRIO_TXD1 VDDSXC Reserved1 Reserved1 GNDSXP SRIO_TXD2/GE1_SGMII_T X GNDSXP SRIO_TXD3/GE2_SGMII_T X GNDSXP MDQ23 VDDDDR MDQ22 MDQ21
MDQS2
Reserved1
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 8 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 F1 F2 F3 F4 F5 F6 F7 F8 F9 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) UTOPIA UTOPIA UTOPIA UTOPIA 1 (001) 2 (010) 3 (011) PCI PCI PCI PCI 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDGE1 VDDGE1 VDDGE1 VDDGE1 VDDGE1 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 -- -- GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDDDDR VDDDDR GND VDDDDR GND VDDDDR -- UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 UTOPIA UTOPIA Ethernet 1 Ethernet 1 PCI PCI UTOPIA UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 GND UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 GND
Signal Name
GE1_RX_CLK/UTP_RD6/ PCI_PAR GE1_RD2/UTP_RD4/ PCI_FRAME GE1_RD1/UTP_RD3/ PCI_CBE3 GE1_RD3/UTP_RD5/ PCI_IRDY VDDGE1 GE1_TX_EN/UTP_TD6/ PCI_CBE0 Reserved1 Reserved1 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDDDDR MDQ20 GND VDDDDR GND MDQS2 Reserved1 GE1_TX_CLK/UTP_RD0/ PCI_AD31 VDDGE1 GE1_TD3/UTP_TD5/ PCI_AD30 GE1_TD1/UTP_TD3/ PCI_AD28 GND GE1_TD0/UTP_TD2/ PCI_AD27 VDDGE1 GND
Ethernet 1 Ethernet 1 Ethernet 1 Ethernet 1
UTOPIA UTOPIA UTOPIA UTOPIA
Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 9
Table 1. Signal List by Ball Number (continued)
Ball Number F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 VDD GND VDD GND VDD GND VDD GND VDD GND VDD Reserved VDDDDR GND MDQ19 MDQ18 MDM2 MDQ17 MDQ16 Reserved1 SRESET4 GND PORESET4 GE1_COL/UTP_RD1 GE1_TD2/UTP_TD4/ PCI_AD29 GE1_RX_DV/UTP_RD7 GE1_TX_ER/UTP_TD7/ PCI_CBE1 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND Reserved1 GND -- UTOPIA UTOPIA UTOPIA UTOPIA Ethernet 1 Ethernet 1 Ethernet 1 Ethernet 1 PCI PCI UTOPIA UTOPIA UTOPIA UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA
1
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDD GND VDD GND VDD GND VDD GND VDD GND VDD -- VDDDDR GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- VDDIO GND VDDIO VDDIO VDDGE1 VDDGE1 VDDGE1 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND -- GND
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 10 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number G23 G24 G25 G26 G27 G28 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 J1 J2 J3 J4 J5 J6 J7 MBA1 MA3 MA8 VDDDDR GND MCK0 Reserved1 CLKIN HRESET PCI_CLK_IN NMI URXD/GPIO14/IRQ8/ RC_LDF3, 6 GE1_RX_ER/PCI_AD6/ GPIO25/IRQ153, 6 GE1_CRS/PCI_AD5 GND VDD GND VDD GND VDD VDD VDD GND VDD GND VDD VDD VDDDDR MBA0 MA15 VDDDDR MA9 MA7 MCK0 Reserved GND VDDIO STOP_BS NMI_OUT4 INT_OUT4 SDA/GPIO27
3, 4, 6 1
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR -- VDDIO VDDIO VDDIO VDDIO
RC_LDF GPIO/ IRQ PCI Ethernet 1 Ethernet 1
UART/GPIO/IRQ PCI PCI GPIO/ IRQ Ethernet 1 Ethernet 1
VDDIO VDDIO VDDIO GND VDD GND VDD GND VDD VDD VDD GND VDD GND VDD VDD VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- GND VDDIO VDDIO VDDIO VDDIO
I2C/GPIO
VDDIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 11
Table 1. Signal List by Ball Number (continued)
Ball Number J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 VDDIO VDD GND VDD GND VDD GND GND GND VDD GND VDD GND GND GND GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 Reserved1 Reserved
1
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDD GND VDD GND VDD GND GND GND VDD GND VDD GND GND GND GND VDDDDR GND VDDDDR GND VDDDDR -- -- -- -- VDDPLL2A GND VDDPLL0A VDDPLL1A VDD GND VDD GND VDD VDD VDD VDD VDD GND VDD GND VDD VDDDDR
Reserved1 VDDPLL2A GND VDDPLL0A VDDPLL1A VDD GND VDD GND VDD VDD VDD VDD VDD GND VDD GND VDD VDDDDR
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 12 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number K23 K24 K25 K26 K27 K28 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 M1 M2 M3 M4 M5 M6 M7 MBA2 MA10 MA12 MA14 MA4 MVREF Reserved1 CLKOUT TMR1/UTP_IR/PCI_CBE3/ GPIO173, 6 TMR4/PCI_PAR/GPIO203, 6/ UTP_REOP GND TMR2/PCI_FRAME/ GPIO183, 6 SCL/GPIO263, 4, 6 UTXD/GPIO15/IRQ93, 6 GND VDD GND VDD GND VDD Reserved VDD GND VDD GND VDD GND GND MCKE1 MA1 VDDDDR GND VDDDDR MCK1 Reserved TRST EE0 EE1 UTP_RCLK/PCI_AD13 UTP_RADDR0/PCI_AD7 UTP_TD8/PCI_AD30 UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA
1 1
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- VDDIO UTOPIA TMR/ GPIO UTOPIA PCI PCI UTOPIA TIMER/GPIO VDDIO VDDIO GND TIMER/GPIO PCI I2C/GPIO UART/GPIO/IRQ TIMER/GPIO UTOPIA VDDIO VDDIO VDDIO GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR -- VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
TIMER/GPIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 13
Table 1. Signal List by Ball Number (continued)
Ball Number M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 VDDIO VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDDDDR MCS1 MA13 MA2 MA0 GND MCK1 Reserved1 VDDIO TMS UTP_RD10/PCI_AD145 VDDIO UTP_RADDR1/PCI_AD8 UTP_TD9/PCI_AD31 TMR3/PCI_IRDY/GPIO193, 6 / UTP_TEOP GND VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 GND UTOPIA UTOPIA PCI PCI PCI UTOPIA PCI Power UTOPIA UTOPIA TIMER/GPIO UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR -- VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 GND
Signal Name
TIMER/GPIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 14 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number N22 N23 N24 N25 N26 N27 N28 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 R1 R2 R3 R4 R5 R6 GND MODT1 MCKE0 VDDDDR MA5 MA6 MA11 Reserved1 TDI5 UTP_RD11/PCI_AD15 GND UTP_RADDR3/PCI_AD10 UTP_RADDR2/PCI_AD9 PCI_GNT/GPIO29/IRQ73. 6 PCI_STOP/GPIO30/IRQ23,
6
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- VDDIO UTOPIA PCI UTOPIA VDDIO GND UTOPIA UTOPIA GPIO/IRQ GPIO/IRQ PCI PCI PCI PCI UTOPIA UTOPIA GPIO/IRQ GPIO/IRQ VDDIO VDDIO VDDIO VDDIO GND GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR GND VDDDDR -- VDDIO VDDIO UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA VDDIO VDDIO VDDIO
GND GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MCS0 MRAS GND VDDDDR GND MCK2 Reserved1 TCK TDO UTP_RD12/PCI_AD16 UTP_RCLAV_PDRPA/ PCI_AD12 UTP_RADDR4/PCI_AD11
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 15
Table 1. Signal List by Ball Number (continued)
Ball Number R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 VDDIO PCI_REQ GND GND GND GND GND GND GND GND GND GND GND GND GND GND MODT0 MDIC1 MDIC0 MCAS MWE MCK2 Reserved1 UTP_RPRTY/PCI_AD21 UTP_RD13/PCI_AD17 VDDIO UTP_RD14/PCI_AD18 UTP_RD15/PCI_AD19 PCI_TRDY PCI_DEVSEL/GPIO31/ IRQ33, 6 GND GND GND GND GND GND GND GND GND GND GND GND GPIO/IRQ PCI UTOPIA UTOPIA PCI PCI PCI GPIO/IRQ UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA PCI PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND GND GND GND GND
Signal Name
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 16 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number T21 T22 T23 T24 T25 T26 T27 T28 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 V1 V2 V3 V4 V5 V6 V7 GND VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 UTP_TCLK/PCI_AD29 UTP_TADDR4/PCI_AD27 UTP_TADDR2 GND UTP_REN/PCI_AD20 PCI_AD26 PCI_AD25 Reserved1 VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND MDQ7 MDQ3 MDQ4 MDQ5 MDQ1 MDQ0 Reserved1 UTP_TD10/PCI_CBE0 UTP_TADDR3 UTP_TD1/PCI_PERR UTP_TADDR0/PCI_AD23 UTP_TADDR1/PCI_AD24 UTP_TCLAV/PCI_AD28 UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI PCI PCI UTOPIA PCI UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR -- VDDIO VDDIO VDDIO GND VDDIO VDDIO VDDIO VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR -- VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
Signal Name
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 17
Table 1. Signal List by Ball Number (continued)
Ball Number V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 VDDIO Reserved1 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MDQ2 VDDDDR MDQ6 GND VDDDDR MDQS0 Reserved1 UTP_TD12/PCI_CBE2 UTP_TD11/PCI_CBE1 VDDIO GND UTP_TD15/PCI_IRDY UTP_TD0/PCI_SERR UTP_RSOC/PCI_AD22 Reserved1 VDDM3 GND V25M3 GND VDDM3 V25M3 VDDM3 GND V25M3 GND VDDM3 GND GND UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR -- VDDIO VDDIO VDDIO GND VDDIO VDDIO VDDIO VDDIO VDDM3 GND V25M3 GND VDDM3 V25M3 VDDM3 GND V25M3 GND VDDM3 GND GND
Signal Name
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 18 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number W23 W24 W25 W26 W27 W28 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 AA1 AA2 AA3 AA4 AA5 AA6 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR GND VDDDDR VDDDDR GND VDDDDR UTOPIA TDM/GPIO TDM TDM TDM RC14 UTOPIA PCI PCI PCI PCI PCI PCI UTOPIA UTOPIA UTOPIA TDM/GPIO TDM TDM TDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR VDDDDR -- UTOPIA TDM/GPIO TDM/GPIO TDM/GPIO PCI PCI PCI PCI UTOPIA TDM/GPIO TDM/GPIO TDM/GPIO VDDIO VDDIO VDDIO VDDIO GND
Signal Name
MDQ10 GND MDQ11 MDM0 GND MDQS0 Reserved1 UTP_TD14/PCI_FRAME TDM5TSYN/PCI_AD18/ GPIO123, 6 TDM5TCLK/PCI_AD16 TDM4RCLK/PCI_AD7 TDM4TSYN/PCI_AD12 UTP_TPRTY/RC14 UTP_TEN/PCI_PAR Reserved1 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MDQ13 VDDDDR GND MDQ9 VDDDDR MDQ8 Reserved1 UTP_TD13/PCI_CBE3 TDM5RSYN/PCI_AD15/ GPIO103, 6 TDM5TD3, AT/PCI_AD17/ GPIO116 TDM5RCLK/PCI_AD13/ GPIO283, 6 GND
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 19
Table 1. Signal List by Ball Number (continued)
Ball Number AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) TDM TDM 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) TDM TDM 7 (111) Ref. Supply VDDIO VDDIO VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR RC15 UTOPIA VDDIO VDDIO TDM/GPIO/ IRQ TDM/GPIO TDM/GPIO/IRQ TDM/GPIO/IRQ TDM TDM PCI PCI PCI PCI PCI PCI TDM/GPIO/ IRQ TDM/GPIO TDM/GPIO/IRQ TDM/GPIO/IRQ TDM TDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND
Signal Name
TDM4TCLK/PCI_AD10 TDM4TDAT/PCI_AD11 VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND MDQ15 MDQ14 MDM1 MDQ12
PCI PCI
MDQS1
MDQS1 Reserved1 UTP_TSOC/RC15 VDDIO TDM6RDAT/PCI_AD20/ GPIO5/IRQ113, 6 TDM5RDAT/PCI_AD14/ GPIO93, 6 TDM6TSYN/PCI_AD24/ GPIO8/ IRQ143, 6 TDM6RCLK/PCI_AD19/ GPIO4/IRQ103, 6 TDM4RSYN/PCI_AD9 TDM4RDAT/PCI_AD8 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 20 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AD1 AD2 AD3 VDDM3 GND GND VDDDDR MECC7 MECC1 MECC4 MECC5 MECC2 ECC_MDQS Reserved1 UTP_RD9/RC13 UTP_RD8/RC12 TDM6TCLK/PCI_AD22 TDM6RSYN/PCI_AD21/ GPIO6/ IRQ123, 6 VDDIO TDM3TSYN/RC11 PCI_AD23/GPIO7/IRQ13/ TDM6TDAT3, 6/UTP_RMOD TDM7TSYN/ PCI_AD4 VDDM3IO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3IO Reserved1 MECC6 MECC3 ECC_MDM VDDDDR MECC0 VDDDDR ECC_MDQS Reserved1 GPIO1
3, 6
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR --
RC13 RC12 TDM TDM/GPIO/IRQ
UTOPIA UTOPIA PCI PCI TDM TDM/GPIO/IRQ
VDDIO VDDIO VDDIO VDDIO VDDIO
RC11 TDM/GPIO/IRQ TDM PCI
TDM PCI TDM/GPIO/IRQ reserved UTOPIA
VDDIO VDDIO VDDIO VDDM3IO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3IO -- VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR --
GPIO TIMER/GPIO
VDDIO VDDIO
TMR0/GPIO13
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 21
Table 1. Signal List by Ball Number (continued)
Ball Number AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) GPIO 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO GND TDM RC10 RC9 RC8 TDM TDM TDM VDDIO VDDIO VDDIO VDDIO GND V25M3 GND VDDM3 GND V25M3 GND VDDM3 GND V25M3 GND
1
Signal Name
GPIO23, 6 GND TDM1TCLK TDM3TDAT/RC10 TDM3RSYN/RC9 TDM3RDAT/RC8 GND V25M3 GND VDDM3 GND V25M3 GND VDDM3 GND V25M3 GND Reserved VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 GPIO03, 6 GPIO33, 6 TDM1RCLK TDM1TSYN/RC3 TDM1TDAT/RC2 TDM1RSYN/RC1 TDM3RCLK/RC16 TDM3TCLK TDM2TDAT/RC6 GPIO21/IRQ13. 6 GND Reserved GND Reserved1 Reserved1 Reserved1 GND
1
-- VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR -- GPIO GPIO TDM RC3 RC2 RC1 RC16 TDM TDM TDM TDM TDM RC6 TDM GPIO/IRQ/SPI_SCK VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND -- GND -- -- -- GND
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 22 Freescale Semiconductor
Table 1. Signal List by Ball Number (continued)
Ball Number AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AF1 AF2 AF3 AF4 GND VDDM3IO Reserved1 GND GND GND VDDDDR GND VDDDDR GND Reserved1 VDDIO GND TDM0RDAT/ RCFG_CLKIN_RNG TDM0TSYN/RCW_SRC2 TDM1RDAT/RC0 VDDIO GND TDM2RDAT/RC4 TDM2TCLK GPIO22/IRQ4 GND GND VDDM3IO GND GND Reserved VDDM3IO GND Reserved1 Reserved
1 1 3, 6
Signal Name
PowerOn Reset Value
I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDM3IO -- GND GND GND VDDDDR GND VDDDDR GND -- VDDIO GND
RCFG_ CLKIN_ RNG RCW_ SRC2 RC0
TDM
VDDIO
AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AG1 AG2 AG3
TDM TDM
VDDIO VDDIO VDDIO GND
RC4
TDM TDM GPIO/IRQ/SPI_MOSI
VDDIO VDDIO VDDIO GND GND VDDM3IO GND GND -- VDDM3IO GND -- -- VDDM3IO GND VDDDDR GND VDDDDR GND VDDDDR --
M3_RESET GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 GPIO16/IRQ03, 6 TDM0TCLK GPIO/IRQ TDM
VDDIO VDDIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 23
Table 1. Signal List by Ball Number (continued)
Ball Number AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 PowerOn Reset Value RCW_ SRC0 I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO -- GND GND GND GND
1
Signal Name
TDM0RSYN/RCW_SRC0 TDM0RCLK TDM0TDAT/RCW_SRC1 TDM2TSYN/RC7 TDM2RCLK TDM2RSYN/RC5 GPIO24/IRQ63, 6 GPIO23/IRQ53, 6 Reserved1 GND GND GND GND Reserved Reserved1 GND GND VDDM3IO GND GND GND VDDDDR GND VDDDDR GND Reserved
1
TDM TDM
RCW_ SRC1 RC7
TDM TDM TDM
RC5
TDM GPIO/IRQ/SPI_SL GPIO/IRQ/SPI_MISO
-- -- GND GND VDDM3IO GND GND GND VDDDDR GND VDDDDR GND -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Reserved1 Reserved1 Reserved1 Reserved
1
Reserved1 Reserved
1
Reserved1 Reserved
1
Reserved1 Reserved
1
Reserved1 Reserved1 Reserved1 Reserved
1
Reserved1
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 24 Freescale Semiconductor
Electrical Characteristics
Table 1. Signal List by Ball Number (continued)
Ball Number AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 Notes: PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply -- -- -- -- -- -- -- -- -- -- -- --
Signal Name
Reserved1 Reserved1 Reserved1 Reserved
1
Reserved1 Reserved
1
Reserved1 Reserved1 Reserved1 Reserved
1
Reserved1 Reserved 1. 2. 3. 4. 5. 6.
1
Reserved signals should be disconnected for compatibility with future revisions of the device. For signals with same functionality in all modes the appropriate cells are empty. The choice between GPIO function and other function is by GPIO registers setup. For configuration details, see Chapter 23, GPIO in the MSC8144 Reference Manual. Open-drain signal. Internal 20 K pull-up resistor. For signals with GPIO functionality, the open-drain and internal 20 K pull-up resistor can be configured by GPIO register programming. See Chapter 23, GPIO of the MSC8144 Reference Manual for configuration details.
2
Electrical Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8144 Reference Manual.
2.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device with a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 25
Electrical Characteristics
Table 2 describes the maximum electrical ratings for the MSC8144. Table 2. Absolute Maximum Ratings
Rating
Core supply voltage PLL supply voltage
Symbol
Vdd VDDPLL0 VDDPLL1 VDDPLL2 VDDM3 VDDDDR
Value
-0.3 to 1.1 -0.3 to 1.1
Unit
V V
M3 memory Internal voltage DDR memory supply voltage * DDR mode * DDR2 mode DDR reference voltage Input DDR voltage Ethernet 1 I/O voltage Input Ethernet 1 I/O voltage Ethernet 2 I/O voltage Input Ethernet 2I/O voltage I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines Input I/O voltage M3 memory I/O and M3 memory charge pump voltage
-0.3 to 1.32 -0.3 to 2.75 -0.3 to 1.98
V V V V V V V V V V V V
MVREF VINDDR VDDGE1 VINGE1 VDDGE2 VINGE2 VDDIO VINIO VDDM3IO V25M3 VINM3IO VDDSXC VDDSXP VDDRIOPLL TJ TSTG
-0.3 to 0.51 x VDDDDR -0.3 to VDDDDR + 0.3 -0.3 to 3.465 -0.3 to VDDGE1 + 0.3 -0.3 to 3.465 -0.3 to VDDGE2 + 0.3 -0.3 to 3.465 -0.3 to VDDIO + 0.3 -0.3 to 2.75
Input M3 memory I/O voltage Rapid I/O C voltage Rapid I/O P voltage Rapid I/O PLL voltage Operating temperature Storage temperature range Notes: 1. 2. 3. 4.
-0.3 to VDDM3IO + 0.3 -0.3 to 1.21 -0.3 to 1.26 -0.3 to 1.21 -40 to 105 -55 to +150
V V V V C C
Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ). PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 26 Freescale Semiconductor
Electrical Characteristics
2.2
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Rating Symbol
VDD VDDPLL0 VDDPLL1 VDDPLL2 VDDM3 VDDDDR 2.375 1.71 0.49 x VDDDDR 2.375 3.135 VDDGE2 2.375 3.135 VDDIO VDDM3IO V25M3 VDDSXC VDDSXP 0.95 1.14 VDDRIOPLL TJ TA TJ 0.95 0 -40 -- 1.0 1.2 1.0 1.05 1.26 1.05 90 -- 105 V V V C C C 3.135 2.375 0.95 2.5 3.3 3.3 2.5 1.0 2.625 3.465 3.465 2.625 1.05 V V V V V 2.5 1.8 0.5 x VDDDDR 2.5 3.3 2.625 1.89 0.51 x VDDDDR 2.625 3.465 V V V V V
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Min
0.97 0.97
Nominal
1.0 1.0
Max
1.05 1.05
Unit
V V
Core supply voltage PLL supply voltage
M3 memory Internal voltage DDR memory supply voltage * DDR mode * DDR2 mode DDR reference voltage Ethernet 1 I/O voltage * 2.5 V mode * 3.3 V mode Ethernet 2 I/O voltage * 2.5 V mode * 3.3 V mode I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines M3 memory I/O and M3 charge pump voltage Rapid I/O C voltage Rapid I/O P voltage * Short run (haul) mode * Long run (haul) mode Rapid I/O PLL voltage Operating temperature range: * Standard * Extended Note:
1.14
1.2
1.26
V
MVREF VDDGE1
PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see Figure 46).
2.3
Default Output Driver Characteristics
Table 4. Output Drive Impedance
Driver Type Output Impedance ()
18 18 35 (half strength mode) 25 100 50
Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
DDR signal DDR2 signal PCI signals Rapid I/O signals Other signals
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 27
Electrical Characteristics
2.4
Thermal Characteristics
Table 5. Thermal Characteristics for the MSC8144
FC-PBGA 29 x 29 mm5 Natural Convection 200 ft/min (1 m/s) airflow
15 12 C/W C/W C/W C/W
Table 5 describes thermal characteristics of the MSC8144 for the FC-PBGA packages.
Characteristic
Symbol
Unit
Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)4 Junction-to-case5 Notes: 1.
1, 3
RJA RJA RJB RJC
20 15 7 0.8
2. 3. 4. 5.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature.
Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.
2.5
Power Characteristics
Table 6. Power Dissipation
Extended Core Frequency 266 Core Frequency 400 533 667 800 333 500 667 833 1000 400 400 600 800 1000 500 500 750 1000 Typical TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD W W W Unit W
The estimated typical power dissipation for MSC8144 versus the core frequency is shown in Table 6.
Note:
Measured for 1.0 V core at 25C junction temperature.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 28 Freescale Semiconductor
Electrical Characteristics
The typical power values were measured using an EFR code with the device running at a junction temperature of 25C. No peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and all four cores. It was created using CodeWarrior(R) 3.0. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of this document. At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AVDD supplies for the MSC8144 PLLs. Table 7. MSC8144 PLLs Power Dissipation
PLL supply VDDPLL0 VDDPLL1 VDDPLL2 Note: Typical TBD TBD TBD Maximum 10 10 10 Unit mW mW mW
Typical value is based on VDD = 1.0 V, TA = 70C, TJ = 105C.
2.6
2.6.1
Note:
DC Electrical Characteristics
DDR SDRAM DC Electrical Characteristics
DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM uses VDDDDR(typ) = 1.8 V.
This section describes the DC electrical characteristics for the MSC8144.
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144.
2.6.1.1
DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144 when VDDDDR(typ) = 1.8 V. Table 8. DDR2 SDRAM DC Electrical Characteristics for VDD(typ) = 1.8 V
Parameter/Condition
I/O supply voltage1 I/O reference voltage2 I/O termination voltage3 Input high voltage Input low voltage Output leakage current4 Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Notes: 1. 2. 3. 4.
Symbol
VDDDDR MVREF VTT VIH VIL IOZ IOH IOL
Min
1.7 0.49 x VDDDDR MVREF - 0.04 MVREF + 0.125 -0.3 -30 -13.4 13.4
Max
1.9 0.51 x VDDDDR MVREF + 0.04 VDD + 0.3
Unit
V V V V V A mA mA
MVREF - 0.125
30 -- --
VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. MVREF is expected to be equal to 0.5 x VDDDDR, and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of VDDDDR. Output leakage is measured with all outputs are disabled, 0 V VOUT VDDDDR.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 29
Electrical Characteristics
Table 9 provides the DDR capacitance when VDDDDR(typ) = 1.8 V. Table 9. DDR2 SDRAM Capacitance for VDDDDR(typ) = 1.8 V
Parameter/Condition
Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note:
Symbol
CIO CDIO
Min
6 --
Max
8 0.5
Unit
pF pF
This parameter is sampled. VDDDDR = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.
2.6.1.2
DDR (2.5V) SDRAM DC Electrical Characteristics
Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144 when VDDDDR(typ) = 2.5 V. Table 10. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V
Parameter/Condition
I/O supply voltage1 I/O reference voltage2
3
Symbol
VDDDDR MVREF VTT VIH VIL
Min
2.3 0.49 x VDDDDR MVREF - 0.04 MVREF + 0.15 -0.3 -30 -16.2 16.2
Max
2.7 0.51 x VDDDDR MVREF + 0.04 VDD + 0.3 MVREF - 0.15 30 -- --
Unit
V V V V V A mA mA
I/O termination voltage Input high voltage Input low voltage
Output leakage current
4
IOZ IOH IOL
Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Notes: 1. 2. 3. 4.
VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. MVREF is expected to be equal to 0.5 x VDDDDR, and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of VDDDDR. Output leakage is measured with all outputs are disabled, 0 V VOUT VDDDDR.
Table 11 provides the DDR capacitance when VDDDDR (typ) = 2.5 V. Table 11. DDR SDRAM Capacitance for VDDDDR (typ) = 2.5 V
Parameter/Condition
Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note:
Symbol
CIO CDIO
Min
6 --
Max
8 0.5
Unit
pF pF
This parameter is sampled. VDDDDR = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.
Table 12 lists the current draw characteristics for MVREF. Table 12. Current Draw Characteristics for MVREF
Parameter / Condition
Current draw for MVREF Note:
Symbol
IMVREF
Min
--
Max
500
Unit
A
The voltage regulator for MVREF must be able to supply up to 500 A current.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 30 Freescale Semiconductor
Electrical Characteristics
2.6.2
Serial RapidIO DC Electrical Characteristics
DC receiver logic levels are not defined since the receiver is AC-coupled.
2.6.2.1
DC Requirements for SerDes Reference Clocks
The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential clock input has an internal 50 termination to GNDSXC. The reference clock must be able to drive this termination. The recommended minimum operating voltage is -0.4 V; the recommended maximum operating voltage is 1.32 V; and the maximum absolute voltage is 1.72 V.
The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is GNDSXC. For example, a clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0-0.8 V). The input is AC-coupled internally, so, therefore, the exact common mode input voltage is not critical. Note: This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz.
If the device driving the SRIO_REF_CLK inputs cannot drive 50 to GNDSXC, or if it exceeds the maximum input current limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V (0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see Figure 5. The termination to GNDSXC allows compatibility with HCSL type reference clocks specified for PCI-Express applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the limited common mode input range. LVPECL outputs can produce too large an amplitude and may need to be source terminated with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV differential peak-peak for single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible with AC-coupling.
SRIO_REF_CLK
50 GNDSXC 50
SRIO_REF_CLK
Figure 5. SerDes Reference Clocks Input Stage
2.6.2.2
Spread Spectrum Clock
SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 31
Electrical Characteristics
2.6.3
* * Note:
PCI DC Electrical Characteristics
TA = 25 C GND = 0 VDC The leakage current is measured for nominal conditions. Table 13. PCI DC Electrical Characteristics
Characteristic Symbol
VDDPCI VIH VIL
2
The measurements in Table 13 assume the following system conditions:
Min
3.135 0.5 x VDDPCI -0.5 0.7 x VDDPCI -10 -10 -10 -10 0.9 x VDDPCI --
Max
3.465 3.465 0.3 x VDDPCI 10 10 10 10 -- 0.1 x VDDPCI 10
Unit
V V V A A A A V V pF
Supply voltage 3.3 V Input high voltage Input low voltage Input Pull-up voltage
VIPU IIN IOZ IL IH VOH VOL CIN
Input leakage current, 02.6.4
* * Note:
TDM DC Electrical Characteristics
TA = 25 C GND = 0 VDC The leakage current is measured for nominal conditions. Table 14. TDM DC Electrical Characteristics
Characteristic Symbol
VDDTDM VIH VIL IIN IOZ IL VOH VOL Cp
The measurements in Table 14 assume the following system conditions:
Min
3.135 2.0 -0.3 -10 -10 -10 2.4 --
Max
3.465 3.465 0.8 10 10 10 -- 0.4 8
Unit
V V V A A A V V pF
Supply voltage 3.3 V Input high voltage Input low voltage Input leakage current, 02.6.5
TBD
UART DC Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 32 Freescale Semiconductor
Electrical Characteristics
2.6.6
* *
Ethernet DC Electrical Characteristics
TA = 25 C GND = 0 VDC
The measurements assume:
2.6.6.1
MII, SMII and RMII DC Electrical Characteristics
Table 15. MII, SMII and RMII DC Electrical Characteristics
Characteristic Symbol
VDDGE1 VDDGE2 VIH VIL IIN IL IH VOH VOL CIN
Min
3.135 2.0 -0.3 -10 -10 -10 2.4 --
Max
3.465 3.465 0.8 10 10 10 3.465 0.4 8
Unit
V V V A A A V V pF
Supply voltage 3.3 V Input high voltage Input low voltage Input leakage current, VIN = supply voltage Signal low input current, VIL = 0.4 V Signal high input current, VIH = 2.4 Output high voltage, IOH = -4 mA, Output low voltage, IOL= 4mA Input Pin Capacitance Note: Not tested. Guaranteed by design.
1
V1
2.6.6.2
RGMII DC Electrical Characteristics
Table 16. RGMII DC Electrical Characteristics
Characteristic Symbol
VDDGE1 VDDGE2 VIH VIL VIH-AC VIL-AC IIN IL
1
Min
2.375 1.7 -0.3 1.9 -- -10 -10 -10 2.0 --
Max
2.625 2.625 0.7 -- 0.7 10 10 10 2.625 0.4 8
Unit
V V V V V A A A V V pF
Supply voltage 2.5V Input high voltage Input low voltage Input high voltage ac Input low voltage ac Input leakage current, VIN = supply voltage Signal low input current, VIL = 0.4 V1
Signal high input current, VIH = 2.4 V Output high voltage, IOH = -1 mA, Output low voltage, IOL= 1 mA Input Pin Capacitance Note:
IH VOH VOL CIN
Not tested. Guaranteed by design.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 33
Electrical Characteristics
2.6.7
ATM/UTOPIA DC Electrical Characteristics
Table 17. ATM/UTOPI DC Electrical Characteristics
Characteristic Symbol
VDDIO VIH VIL IIN IL IH VOH VOL
1
Min
3.135 2.0 -0.3 -10 -10 -10 2.4 --
Max
3.465 3.465 0.8 10 10 10 3.465 0.5
Unit
V V V A A A V V
Supply voltage 3.3 V Input high voltage Input low voltage Input leakage current, VIN = supply voltage Signal low input current, VIL = 0.4 V Signal high input current, VIH = 2.4 V1 Output high voltage, IOH = -8 mA, Output low voltage, IOL= 8 mA Notes: 1. Not tested. Guaranteed by design.
2.6.8
SPI DC Electrical Characteristics
Table 18. SPI DC Electrical Characteristics
Characteristic Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 18 provides the SPI DC electrical characteristics.
Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage
2.6.9
*
GPIO, EE, CLKIN, JTAG Ports DC Electrical Characteristics
TA = 25 C
GND
The measurements in Table 19 assume:
*
Note:
= 0 VDC
The leakage current is measured for nominal conditions. Table 19. GPIO and CLKIN DC Electrical Characteristics
Characteristic Symbol
VDDIO IIN IOZ IL IH VOH
Min
3.135 -10 -10 -10 -10 2.4
Max
3.465 10 10 10 10 3.465
Unit
V A A A A V
Supply voltage 3.3 V Input leakage current, VIN = supply voltage Tri-state (high impedance off state) leakage current, VIN = supply voltage Signal low input current, VIL = 0.4 V
2
Signal high input current, VIH = 2.0 V2 Output high voltage, IOH = -2 mA, except open drain pins
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 34 Freescale Semiconductor
Electrical Characteristics
Table 19. GPIO and CLKIN DC Electrical Characteristics (continued)
Characteristic
Output low voltage, IOL= 3.2 mA Notes: 1. 2. See Figure 6 for undershoot and overshoot voltages. Not tested. Guaranteed by design.
Symbol
VOL
Min
--
Max
0.4
Unit
V
VIH
VDDIO + 17% VDDIO + 5% VDDIO
VIL
GND GND - 0.3 V GND - 0.7 V
Must not exceed 10% of clock period
Figure 6. Overshoot/Undershoot Voltage for VIH and VIL
2.7
2.7.1
AC Timings
Start-Up Timing
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2 describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8144 device: * PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V) supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion. During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp. For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information. CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation (see Figure 7). 32 cycles should be accounted only after VDDIO reaches its nominal value. CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows during power-up.
Note: * *
Figure 7 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 35
Electrical Characteristics
VDDIO = Nominal
VDD = Nominal
1
3.3 V
VDDIO Nominal
Voltage
1.0 V
VDD Nominal
Time
PORESET/TRST asserted VDD applied CLKIN starts toggling PORESET
VDDIO applied
Figure 7. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
2.7.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that maximum frequency values are not exceeded. Table 20. Clock Frequencies
Characteristic
CLKIN frequency PCI_CLK_IN frequency CLKIN duty cycle PCI_CLK_IN duty cycle
Symbol
FCLKIN FPCI_CLK_IN DCLKIN DPCI_CLK_IN
MIN
25 25 40 40
Max
150 150 60 60
Unit
MHz MHz % %
Table 21. Clock Parameters
Characteristic
CLKIN slew rate PCI_CLK_IN slew rate
Min
1 1
Max
-- --
Unit
V/ns V/ns
2.7.3
* * * * * * * *
Reset Timing
Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Software watchdog reset JTAG reset RapidIO reset Software hard reset Software soft reset
The MSC8144 has several inputs to the reset logic:
All MSC8144 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 36 Freescale Semiconductor
Electrical Characteristics
Table 22. Reset Sources
Name Power-on reset (PORESET) Direction Input Description Initiates the power-on reset flow that resets the MSC8144 and configures various attributes of the MSC8144. On PORESET, the entire MSC8144 device is reset. All PLLs states is reset, HRESET and SRESET are driven, the extended cores are reset, and system configuration is sampled. The reset source and word are configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC8144. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144 Reference Manual. Initiates the soft reset flow. The MSC8144 detects an external assertion of SRESET only if it occurs while the MSC8144 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the extended cores are reset, and system configuration is maintained. When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated. When the MSC8144 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset sequence. A hard reset sequence can be initialized by writing to a memory mapped register (RCR) A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
External hard reset (HRESET)
Input/ Output
External soft reset (SRESET) Host reset command through the TAP Software watchdog reset RapidIO reset Software hard reset Software soft reset
Input/ Output
Internal
Internal Internal Internal Internal
Table 23 summarizes the reset actions that occur as a result of the different reset sources. Table 23. Reset Actions for Each Reset Source
Power-On Reset (PORESET) Reset Action/Reset Source External only Configuration pins sampled (Refer to Section 2.7.3.2 for details). PLL state reset Select reset configuration source System reset configuration write HRESET driven IPBus modules reset (TDM, UART, SWT, DDRC, IPBus master, GIC, HS, and GPIO) SRESET driven Extended cores reset CLASS registers reset Timers, Performance Monitor Packet Processor, PCI, DMA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes External or Internal (Software Watchdog, Software or RapidIO) No No No No Yes Yes Yes Yes Yes Yes Yes External or internal Software No No No No No Yes Yes Yes Some registers No Most registers JTAG Command: EXTEST, CLAMP, or HIGHZ No No No No No Yes Depends on command Yes Some registers No Most registers Hard Reset (HRESET) Soft Reset (SRESET)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 37
Electrical Characteristics
2.7.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 32 CLKIN cycles after VDD and VDDIO are both at their nominal levels.
2.7.3.2
* * *
Reset Configuration
The MSC8144 has two mechanisms for writing the reset configuration: Through the I2C port Through external pins Through internal hard coded
Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the Reset Word Configuration Source and operating conditions: * * RCW_SRC[2-0] RC[16-0]
The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid and is also sampled during power-on reset sequence for RCW loading from an I2C EEPROM.
2.7.3.3 Reset Timing Tables
Table 24 and Figure 8 describe the reset timing for a reset configuration. Table 24. Timing for a Reset Configuration Write
No.
1
Characteristics
Required external PORESET duration minimum * 25 MHz <= CLKIN < 44 MHz * 44 MHz <= CLKIN < 66 MHz * 66 MHz <= CLKIN < 100 MHz * 100 MHz <= CLKIN < 133 MHz Delay from de-assertion of external PORESET to HRESET deassertion for external pins and hard coded RCW * 25 MHz <= CLKIN < 66 MHz * 66 MHz <= CLKIN <= 133 MHz Delay from de-assertion of external PORESET to HRESET deassertion for loading RCW the I2C interface * 25 MHz <= CLKIN < 44 MHz * 44 MHz <= CLKIN < 66 MHz * 66 MHz <= CLKIN < 100 MHz * 100 MHz <= CLKIN < 133 MHz
Expression
32/CLKIN
Max
1280 728 485 320
Min
727 484 320 241
Unit
ns ns ns ns
2
15369/CLKIN 34825/CLKIN
615 528
233 262
s s
92545/CLKIN 107435/CLKIN 124208/CLKIN 157880/CLKIN 16/CLKIN
3702 2441 1882 1579 640
2103 1627 1242 1187 120
s s s s ns
3 Note:
Delay from HRESET deassertion to SRESET deassertion * REFCLK = 25 MHz to 133 MHz Timings are not tested, but are guaranteed by design.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 38 Freescale Semiconductor
Electrical Characteristics
RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG
1
pins must be valid
PORESET Input HRESET Output (I/O)
2
SRESET Output (I/O) Reset configuration write sequence during this period.
3
Figure 8. Timing for a Reset Configuration Write
See also Reset Errata for PLL lock and reset duration.
2.7.4
DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.7.4.1
DDR SDRAM Input Timings
Table 22. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter Symbol VIL VIH Min -- MVREF + 0.31 Max MVREF - 0.31 -- Unit V V
Table 22 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 2.5 V.
AC input low voltage AC input high voltage Note: At recommended operating conditions with VDD of 2.5 5%.
Table 23 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 1.8 V. Table 23. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter AC input low voltage AC input high voltage Note: At recommended operating conditions with VDD of 1.8 5%. Symbol VIL VIH Min -- VREF + 0.25 Max VREF - 0.25 -- Unit V V
Table 24 provides the input AC timing specifications for the DDR SDRAM interface. Table 24. DDR SDRAM Input AC Timing Specifications
Parameter Controller Skew for MDQS--MDQ/MECC/MDM * 400 MHz * 333 MHz * 266 MHz * 200 MHz Notes: 1. 2.
1
Symbol tCISKEW
Min -365 -390 -428 -490
Max 365 390 428 490
Unit ps ps ps ps
tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. Subtract this value from the total timing budget. At recommended operating conditions with VDD (1.8 V or 2.5 V) 5%
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 39
Electrical Characteristics
2.7.4.2
DDR SDRAM Output AC Timing Specifications
Table 25. DDR SDRAM Output AC Timing Specifications
Parameter Symbol 1 tMCK tDDKHAS 1.95 2.40 3.15 4.20 tDDKHAX 1.95 2.40 3.15 4.20 tDDKHCS 1.95 2.40 3.15 4.20 tDDKHCX 1.95 2.40 3.15 4.20 tDDKHMH tDDKHDS, tDDKLDS -0.6 700 900 1100 1200 700 900 1100 1200 -0.5 x tMCK - 0.6 -0.6 -- -- -- -- 0.6 -- -- -- -- -- -- -- -- -0.5 x tMCK +0.6 0.6 ns ns ns ns ns ps ps ps ps ps ps ps ps ns ns -- -- -- -- ns ns ns ns -- -- -- -- ns ns ns ns -- -- -- -- ns ns ns ns Min 3 Max 10 Unit ns crossing)2
Table 25 provides the output AC timing specifications for the DDR SDRAM interface.
MCK[n] cycle time, (MCK[n]/MCK[n]
ADDR/CMD output setup with respect to MCK3 * 400 MHz * 333 MHz * 266 MHz * 200 MHz ADDR/CMD output hold with respect to MCK3 * 400 MHz * 333 MHz * 266 MHz * 200 MHz MCSn output setup with respect to MCK3 * 400 MHz * 333 MHz * 266 MHz * 200 MHz MCSn output hold with respect to MCK3 * 400 MHz * 333 MHz * 266 MHz * 200 MHz MCK to MDQS Skew4 MDQ/MECC/MDM output setup with respect to MDQS5 * 400 MHz * 333 MHz * 266 MHz * 200 MHz MDQ/MECC/MDM output hold with respect to MDQS5 * 400 MHz * 333 MHz * 266 MHz * 200 MHz MDQS preamble start6 MDQS epilogue end6 Notes: 1.
tDDKHDX, tDDKLDX
tDDKHMP tDDKHME
2. 3.
4.
5. 6. 7.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. At recommended operating conditions with VDD (1.8 V or 2.5 V) 5%.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 40 Freescale Semiconductor
Electrical Characteristics
Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns
MDQS tDDKHMH(min) = -0.6 ns
MDQS
Figure 9. Timing for tDDKHMH Figure 10 shows the DDR SDRAM output timing diagram.
MCK[n] MCK[n] tMCK tDDKHAS, tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 10. DDR SDRAM Output Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 41
Electrical Characteristics
Figure 11 provides the AC test load for the DDR bus.
Output Z0 = 50 VDD/2
RL = 50
Figure 11. DDR AC Test Load
2.7.5
2.7.5.1
Serial RapidIO Timing and SGMII Timing
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 26. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Table 26 lists AC requirements.
Parameter Description REFCLK cycle time
Symbol tREF
Min --
Typical 10 (8, 6.4)
Max --
Units ns
Comments 8 ns applies only to serial RapidIO system with 125-MHz reference clock. 6.4 ns applies only to serial RapidIO systems with a 156.25 MHz reference clock. Note: SGMII uses the 8 ns (125 MHz) value only. Difference in the period of any two adjacent REFCLK cycles Deviation in edge location with respect to mean edge location
REFCLK cycle-to-cycle jitter Phase jitter
tREFCJ tREFPJ
-- -40
-- --
80 40
ps ps
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 42 Freescale Semiconductor
Electrical Characteristics
2.7.5.2
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential signals. Figure 12 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.
TD or RD
A
B
TD or RD
Differential Peak-Peak = 2 x (A - B)
Figure 12. Differential VPP of Transmitter or Receiver Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/ SRIO_RXD/SRIO_RXD respectively. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage (VPP) swing of A - B. The differential output signal of the transmitter, VOD, is defined as VTD - VTD. The differential input signal of the receiver, VID, is defined as VRD - VRD. The differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B). The peak value of the differential transmitter output signal and the differential receiver input signal is A - B. The value of the differential transmitter output signal and the differential receiver input signal is 2 x (A - B) VPP.
Using these waveforms, the definitions are as follows: 1. 2. 3. 4. 5. 6.
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mVPP. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVPP. Note: AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEETM Std 802.3ae-2002TM. XAUI has similar application goals to serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.
2.7.5.3
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The most common equalization techniques that can be used are: * * A passive high pass filter network placed at the receiver. This is often referred to as passive equalization. The use of active circuits in the receiver. This is often referred to as adaptive equalization.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 43
Electrical Characteristics
2.7.5.4
Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than * * -10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and -10 dB + 10log(f/625 MHz) dB for 625 MHz freq(f) baud frequency
The reference impedance for the differential return loss measurements is 100 resistive. Differential return loss includes contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance requirement applies to all valid output levels. It is recommended that the 20-80% rise/fall time of the transmitter, as measured at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB. Table 27. Short Run Transmitter AC Timing Specifications--1.25 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 800 -0.40 500 Max 2.30 1000 0.17 0.35 1000 800 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Table 28. Short Run Transmitter AC Timing Specifications--2.5 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple Output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 400 -0.40 500 Max 2.30 1000 0.17 0.35 1000 400 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Table 29. Short Run Transmitter AC Timing Specifications--3.125 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 320 -0.40 500 Max 2.30 1000 0.17 0.35 1000 320 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 44 Freescale Semiconductor
Electrical Characteristics
Table 30. Long Run Transmitter AC Timing Specifications--1.25 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 800 -0.40 800 Max 2.30 1600 0.17 0.35 1000 800 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Table 31. Long Run Transmitter AC Timing Specifications--2.5 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 400 -0.40 800 Max 2.30 1600 0.17 0.35 1000 400 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Table 32. Long Run Transmitter AC Timing Specifications--3.125 GBaud
Range Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval Symbol Min VO VDIFFPP JD JT SMO UI 320 -0.40 800 Max 2.30 1600 0.17 0.35 1000 320 V mVPP UIPP UIPP ps ps Skew at the transmitter output between lanes of a multilane link 100 ppm Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in Figure 13 with the parameters specified in Table 33 when measured at the output pins of the device and the device is driving a 100 5% differential resistive load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 45
Electrical Characteristics
Transmitter Differential Output Voltage
VDIFF max VDIFF min
0
-VDIFF min
-VDIFF max
0
A
B Time in UI
1-B
1-A
1
Figure 13. Transmitter Output Compliance Mask Table 33. Transmitter Differential Output Eye Diagram Parameters
Transmitter Type 1.25 GBaud short range 1.25 GBaud long range 2.5 GBaud short range 2.5 GBaud long range 3.125 GBaud short range 3.125 GBaud long range VDIFFmin (mV) 250 400 250 400 250 400 VDIFFmax (mV) 500 800 500 800 500 800 A (UI) 0.175 0.175 0.175 0.175 0.175 0.175 B (UI) 0.39 0.39 0.39 0.39 0.39 0.39
2.7.5.5
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8 x baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 resistive for differential return loss and 25 resistive for common mode. Table 34. Receiver AC Timing Specifications--1.25 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Symbol Min VIN JD JDR 200 0.37 0.55 Max 1600 mVPP UIPP UIPP Measured at receiver Measured at receiver Measured at receiver Unit Notes
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 46 Freescale Semiconductor
Electrical Characteristics
Table 34. Receiver AC Timing Specifications--1.25 GBaud (continued)
Range Characteristic Total Jitter Tolerance Symbol Min JT 0.65 Max UIPP Measured at receiver. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 14. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Skew at the receiver input between lanes of a multilane link 100 ppm Unit Notes
Multiple Input Skew Bit Error Rate Unit Interval
SMI BER UI 800
24 10-12 800
ns
ps
Table 35. Receiver AC Timing Specifications--2.5 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Symbol Min VIN JD JDR JT 200 0.37 0.55 0.65 Max 1600 mVPP UIPP UIPP UIPP Measured at receiver Measured at receiver Measured at receiver Measured at receiver. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 14. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Skew at the receiver input between lanes of a multilane link 100 ppm Unit Notes
Multiple Input Skew Bit Error Rate Unit Interval
SMI BER UI 400
24 10-12 400
ns
ps
Table 36. Receiver AC Timing Specifications--3.125 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Symbol Min VIN JD JDR JT 200 0.37 0.55 0.65 Max 1600 mVPP UIPP UIPP UIPP Measured at receiver Measured at receiver Measured at receiver Measured at receiver. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 14. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Skew at the receiver input between lanes of a multilane link Unit Notes
Multiple Input Skew
SMI
22
ns
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 47
Electrical Characteristics
Table 36. Receiver AC Timing Specifications--3.125 GBaud (continued)
Range Characteristic Bit Error Rate Unit Interval Symbol Min BER UI 320 Max 10-12 320 ps 100 ppm Unit Notes
8.5 UI p-p
Sinusoidal Jitter Amplitude
0.10 UI p-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 14. Single Frequency Sinusoidal Jitter Limits
2.7.5.6
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification (Table 34, Table 35, and Table 36) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 15 with the parameters specified in Table 37. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 5% differential resistive load.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 48 Freescale Semiconductor
Electrical Characteristics
VDIFF max
Receiver Differential Input Voltage
VDIFF min 0 -VDIFF min
-VDIFF max
0
A
B Time (UI)
1-B
1-A
1
Figure 15. Receiver Input Compliance Mask Table 37. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type 1.25 GBaud 2.5 GBaud 3.125 GBaud VDIFFmin (mV) 100 100 100 VDIFFmax (mV) 800 800 800 A (UI) 0.275 0.275 0.275 B (UI) 0.400 0.400 0.400
2.7.5.7
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std. 802.3ae-2002TM, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test methods.
2.7.5.8
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12. The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 resistive 5% differential to 2.5 GHz.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 49
Electrical Characteristics
2.7.5.9
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std. 802.3ae.
2.7.5.10
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100 resistive 5% differential to 2.5 GHz.
2.7.5.11
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in Figure 15 and Table 37. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.7.6
PCI Timing
Table 38. PCI AC Timing Specifications
33 MHz Parameter Symbol Min Max 11.0 -- 28 -- -- -- 40 -- -- Min 1.0 1.0 -- 3.0 0 100 -- 1 32M Max 6.0 -- 14 -- -- -- 40 -- -- ns ns ns ns ns s ns ms clocks tPCVAL tPCON tPCOFF tPCSU tPCH tPCRST-CLK tPCRST-OFF tPCRST tPCRHFA 2.0 2.0 -- 7.0 0 100 -- 1 32M 66 MHz Unit
This section describes the general AC timing parameters of the PCI bus. Table 38 provides the PCI AC timing specifications.
Output delay High-Z to Valid Output delay Valid to High-Z Output delay Input setup Input hold Reset active time after PCI_CLK_IN stable Reset active to output float delay Reset active time after power stable HRESET high to first Configuration Access Notes: 1. 2. 3. 4. 5.
See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x OVDD of the signal in question for 3.3-V PCI signaling levels. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Input timings are measured at the pin. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 50 Freescale Semiconductor
Electrical Characteristics
Figure 16 provides the AC test load for the PCI.
Output
Z0 = 50
RL = 50
VDD/2
Figure 16. PCI AC Test Load Figure 17 shows the PCI input AC timing conditions.
CLK tPCSU tPCH Input
Figure 17. PCI Input AC Timing Measurement Conditions Figure 18 shows the PCI output AC timing conditions.
CLK tPCVAL Output Delay tPCOFF tPCON High-Impedance Output
Figure 18. PCI Output AC Timing Measurement Condition
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 51
Electrical Characteristics
2.7.7
TDM Timing
Table 39. TDM Timing
Characteristic Symbol tTDMC tTDMCH tTDMCL tTDMVKH tTDMXKH tTDMDHOX tTDMDHOV tTDMHOX tTDMDHOZ tTDMSHOV tTDMSHOX Expression TC1 (0.5 0.1) x TC (0.5 0.1) x TC Min 16 7 7 3.6 1.9 2.5 -- 2.5 -- -- 1.6 Max -- -- -- -- -- -- 9.8 -- 9.8 9.25 -- Units ns ns ns ns ns ns ns ns ns ns ns
TDMxRCLK/TDMxTCLK TDMxRCLK/TDMxTCLK high pulse width TDMxRCLK/TDMxTCLK low pulse width TDM receive all input set-up time related to TDMxRCLK TDMxTSYN input set-up time related to TDMxTCLK in TSO=0 mode TDM receive all input hold time related to TDMxRCLK TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode TDMxTCLK high to TDMxTDAT output active2 TDMxTCLK high to TDMxTDAT output valid2 All output hold time (except TDMxTSYN) 3 TDMxTCLK high to TDMxTDAT output high impedance2 TDMxTCLK high to TDMxTSYN output valid2 TDMxTSYN output hold time3 Notes: 1. 2. 3.
Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz. Values are based on 20 pF capacitive load. Values are based on 10 pF capacitive load.
Figure 19 shows the TDM input AC timing.
tTDMC tTDMCH TDMxRCLK tTDMXKH tTDMVKH TDMxRDAT tTDMXKH tTDMCL
tTDMVKH TDMxRSYN
Figure 19. TDM Inputs Signals Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well. See the MSC8144 Reference Manual. Figure 20 shows TDMxTSYN AC timing in TSO=0 mode.
TDMxTCLK tTDMVKH TDMxTSYN tTDMXKH
Figure 20. TDMxTSYN in TSO=0 mode Figure 21 shows the TDM Output AC timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 52 Freescale Semiconductor
tTDMC tTDMCH TDMxTCLK tTDMCL tTDMDHOZ
~~ ~~
tTDMDHOV TDMxTDAT tTDMDHOX
tTDMHOX
tTDMSHOV TDMxTSYN
tTDMSHOX
Figure 21. TDM Output Signals
Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144 Reference Manual
2.7.8
UART Timing
Table 40. UART Timing
Characteristics Symbol TUREFCLK TUAVKH TUAVXH Expression 16 x TREFCLK Min 160 Max -- 6 5.5 Unit ns ns ns
URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time Note: TUREFCLK = TREFCLK is guaranteed by design.
Figure 22 shows the UART input AC timing
TUAVKH UTXD, URXD inputs TUREFCLK TUREFCLK TUAVKH
Figure 22. UART Input Timing Figure 23 shows the UART output AC timing
TUAVXH UTXD output
TUAVXH
Figure 23. UART Output Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 53
2.7.9
Timer Timing
Table 41. Timer Timing
Characteristics Symbol TTMREFCLK TTMCH TTMCL Min 10.0 4.0 4.0 Unit ns ns ns
TIMERx frequency TIMERx Input high phase TIMERx Output low phase
Figure 24 shows the timer input AC timing
TTMREFCLK TTMCH TTMCL
TIMERx (Input)
Figure 24. Timer Timing
2.7.10
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface. There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144 Reference Manual.
2.7.10.1
Management Interface Timing
Table 42. Ethernet Controller Management Interface Timing
Characteristics Symbol tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min 32 10 5 0 -- -- Max -- 70 -- -- 10 10 Unit ns ns ns ns ns ns
ETHMDC clock pulse width high ETHMDC to ETHMDIO delay2 ETHMDIO to ETHMDC rising edge set-up time ETHMDC rising edge to ETHMDIO hold time ETHMDC rise time. ETHMDC fall time. Notes: 1.
2.
Typical ETHMDC frequency (fMDC) is 2.5 MHz with a 400 ns period (tMDC). The value depends on the source clock. For example, for a source clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz. For a 375 MHz clock, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of 333 MHz, the delay is 58 ns.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 54 Freescale Semiconductor
tMDC
tMDCR
ETHMDC
tMDCH tMDHF
ETHMDIO (Input)
tMDDVKH tMDDXKH
ETHMDIO (Output)
tMDKHDX
Figure 25. MII Management Interface Timing
2.7.10.2
MII Transmit AC Timing Specifications
Table 43. MII Transmit AC Timing Specifications
Parameter/Condition Symbol 1 tMTXH/tMTX tMTKHDX tMTXR tMTXF Min 35 0 1.0 1.0 Max 65 25 4.0 4.0 Unit % ns ns ns
Table 43 provides the MII transmit AC timing specifications.
TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise TX_CLK data clock fall Notes: 1. 2.
Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns. Program GCR4 as 0x00030CC3.
Figure 26 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 26. MII Transmit AC Timing
2.7.10.3
MII Receive AC Timing Specifications
Table 44. MII Receive AC Timing Specifications
Parameter/Condition Symbol 1 tMRXH/tMRX Min 35 Max 65 Unit %
Table 44 provides the MII receive AC timing specifications.
RX_CLK duty cycle
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 55
Table 44. MII Receive AC Timing Specifications (continued)
Parameter/Condition RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise RX_CLK clock fall time Notes: 1. 2. Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns. Program GCR4 as 0x00030CC3. Symbol 1 tMRDVKH tMRDXKH tMRXR tMRXF Min 10.0 2 1.0 1.0 Max -- -- 4.0 4.0 Unit ns ns ns ns
Figure 27 provides the AC test load.
Output
Z0 = 50
RL = 50
VDD/2
Figure 27. AC Test Load Figure 28 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR
Figure 28. MII Receive AC Timing
2.7.10.4
RMII Transmit and Receive AC Timing Specifications
Table 45. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition Symbol 1 tRMXH/tRMX tRMTKHDX tRMRDVKH tRMRDXKH tRMXR tRMXF Min 35 2 4.0 2.0 1.0 1.0 Max 65 10 -- -- 4.0 4.0 Unit % ns ns ns ns ns
Table 45 provides the RMII transmit and receive AC timing specifications.
REF_CLK duty cycle REF_CLK to RMII data TXD[1-0], TX_EN delay RXD[1-0], CRS_DV, RX_ER setup time to REF_CLK RXD[1-0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK data clock rise REF_CLK data clock fall Typical REF_CLK clock period (tRMX) is 20 ns Notes: 1. 2. Typical REF_CLK clock period (tRMX) is 20 ns Program GCR4 as 0x00001405
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 56 Freescale Semiconductor
Figure 29 shows the RMII transmit and receive AC timing diagram.
tRMX REF_CLK tRMXH TXD[1-0] TX_EN tRMTKHDX RXD[1-0] CRS_DV RX_ER tRMRDVKH tRMRDXKH Valid Data tRMXF tRMXR
Figure 29. RMII Transmit and Receive AC Timing Figure 30 provides the AC test load.
Output
Z0 = 50
RL = 50
VDD/2
Figure 30. AC Test Load
2.7.10.5
SMII AC Timing Specification
Table 46. SMII Mode Signal Timing
Characteristics Symbol tSMDVKH tSMDXKH tSMXR Min 1.5 1.0 1.5 Max -- -- 5.0 Unit ns ns ns
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay Notes: 1. 2. 3. 4. 5. Typical REF_CLK clock period is 8ns Measured using a 5 pF load. Measured using a 15 pF load REF_CLK duty cycle is TBD. Program GCR4 as 0x00002008
Figure 31 provides the AC test load.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 57
ETHCLOCK tSMDVKH ETHSYNC_IN ETHRXD tSMDXKH
Valid
tSMXR ETHSYNC ETHTXD Valid Valid
Figure 31. SMII Mode Signal Timing
2.7.10.6
RGMII AC Timing Specifications
Table 47. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition Symbol tSKEWT tSKEWR tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12 6 tG125H/tG125 Min -0.5 0.9 7.2 45 40 -- -- -- 47 Typ -- -- 8.0 50 50 -- -- 8.0 -- Max 0.5 2.6 8.8 55 60 0.75 0.75 -- 53 Unit ns ns ns % % ns ns ns %
Table 47 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 2 Clock cycle duration 3 Duty cycle for 1000Base-T 4, 5 Duty cycle for 10BASE-T and 100BASE-TX 3, 5 Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle Notes: 1. 2. 3. 4.
5. 6. 7.
At recommended operating conditions with LVDD of 2.5 V +/- 5%. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. Duty cycle reference is LVdd/2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. GCR4 should be programmed as 0x00001004.
Table 48 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 48. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration 3 Duty cycle for 1000Base-T 4, 5 Duty cycle for 10BASE-T and 100BASE-TX 3, 5 Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period
2
Symbol tSKEWT tSKEWR tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12
6
Min 0.9 -0.5 7.2 45 40 -- -- --
Typ -- -- 8.0 50 50 -- -- 8.0
Max 2.6 0.5 8.8 55 60 0.75 0.75 --
Unit ns ns ns % % ns ns ns
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 58 Freescale Semiconductor
Table 48. RGMII with No On-Board Delay AC Timing Specifications (continued)
Parameter/Condition GTX_CLK125 reference clock duty cycle Notes: 1. 2. 3. 4. Symbol tG125H/tG125 Min 47 Typ -- Max 53 Unit %
5. 6. 7.
At recommended operating conditions with LVDD of 2.5 V +/- 5%. This implies that PC board design will require clocks to be routed with no additional trace delay For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. Duty cycle reference is LVdd/2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. GCR4 should be programmed as 0x00048120.
Figure 32 shows the RGMII AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKEWT TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4]
TX_CTL
TXD[4] TXEN
TXD[9] TXERR tSKEWR
TX_CLK (At PHY)
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[3:0]
RXD[8:5] RXD[7:4] tSKEWT
RX_CTL
RXD[4] RXDV
RXD[9] RXERR tSKEWR
RX_CLK (At PHY)
Figure 32. RGMII AC Timing and Multiplexing s
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 59
2.7.11
ATM/UTOPIA Timing
Table 49. UTOPIA AC Timing Specifications
Characteristic Symbol tUEKHOV tUEKHOX tUEIVKH tUEIXKH Min 1 1 4 1 Max 9 9 Unit ns ns ns ns
Table 49 provides the UTOPIA input and output AC timing specifications.
UTOPIA outputs--External clock delay UTOPIA outputs--External clock High Impedance UTOPIA inputs--External clock input setup time UTOPIA inputs--External clock input hold time Note:
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 33 provides the AC test load for the UTOPIA.
Z0 = 50
Output
RL = 50
VDD/2
Figure 33. UTOPIA AC Test Load Figure 34 shows the UTOPIA timing with external clock.
UTOPIA CLK (input) tUEIVKH tUEIXKH
Input Signals: UTOPIA
Output Signals: UTOPIA
tUEKHOV
tUEKHOX
Figure 34. UTOPIA AC Timing (External Clock) Figure 35 shows the UTOPIA timing with internal clock.
UTOPIA CLK (output) tUIIVKH tUIIXKH
Input Signals: UTOPIA
Output Signals: UTOPIA
tUIKHOV
tUIKHOX
Figure 35. UTOPIA AC Timing (Internal Clock)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 60 Freescale Semiconductor
2.7.12
SPI Timing
Table 50. SPI AC Timing Specifications 1
Characteristic Symbol 2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH tNEIVKH tNEIXKH 2 4 0 4 2 0.5 8 Min Max 6 Unit ns ns ns ns ns ns ns ns
Table 49 provides the SPI input and output AC timing specifications.
SPI outputs valid--Master mode (internal clock) delay SPI outputs hold--Master mode (internal clock) delay SPI outputs valid--Slave mode (external clock) delay SPI outputs hold--Slave mode (external clock) delay SPI inputs--Master mode (internal clock input setup time SPI inputs--Master mode (internal clock input hold time SPI inputs--Slave mode (external clock) input setup time SPI inputs--Slave mode (external clock) input hold time
Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal. Timings are measured at the pin. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 36 provides the AC test load for the SPI.
Output Z0 = 50 OVDD/2
RL = 50
Figure 36. SPI AC Test Load Figure 37 through Figure 38 represent the AC timings from Table 49. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 37 shows the SPI timings in slave mode (external clock).
SPICLK (Input) tNEIVKH tNEIXKH
Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note)
tNEKHOX
Note: The clock edge is selectable on SPI.
Figure 37. SPI AC Timing in Slave Mode (External Clock) Figure 38 shows the SPI timings in master mode (internal clock).
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 61
SPICLK (Output) tNIIVKH tNIIXKH
Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note)
tNIKHOX
Note: The clock edge is selectable on SPI.
Figure 38. SPI AC Timing in Master Mode (Internal Clock)
2.7.13
GPIO Timing
Table 51. GPIO Timing
Characteristics Symbol tGPKHOV tGPKHOX tGPKHOZ tGPIVKH tGPIXKH Min 1.3 3.7 0.5 Max 6.9 6.2 Unit ns ns ns ns ns
REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid (GPIO out hold time) REFCLK edge to high impedance on GPIO out GPIO in valid to REFCLK edge (GPIO in set-up time) REFCLK edge to GPIO in not valid (GPIO in hold time)
Figure 39 shows the GPIO timing.
REFCLK
tGPKHOV tGPKHOZ
GPIO (Output)
High Impedance
tGPIVKH
tGPIXKH
GPIO (Input)
Valid
Figure 39. GPIO Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 62 Freescale Semiconductor
2.7.14
EE Signals
Table 52. EE Pin Timing
Characteristics Symbol tEEIN tEEOUT Type Asynchronous Synchronous to Core clock Min 4 core clock periods 1 core clock period
EE (input) EE (output) Notes: 1. 2.
The ratio between the core clock and CLKOUT is configured during power-on-reset. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 40 shows the signal behavior of the EE pins.
tEEIN EE in
tEEOUT EE out
Figure 40. EE Pin Timing
2.7.14.1
JTAG Signals
Table 53. JTAG Timing
All frequencies Characteristics Symbol Min Max -- -- 3.0 -- -- 20.0 24.0 -- -- 10.0 12.0 -- ns ns ns ns ns ns ns ns ns ns ns ns tTCKX tTCKH tTCKR tBSVKH tBSXKH tTCKHOV tTCKHOZ tTDIVKH tTDIXKH tTDOHOV tTDOHOZ tTRST 33.0 13.0 -- 0.0 10.0 -- -- 0.0 5.0 -- -- 100.0 Unit
TCK cycle time TCK clock high phase measured at VM = 1.6 V TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK fall to output data valid TCK fall to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK fall to TDO data valid TCK fall to TDO high impedance TRST assert time Note:
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 41 Shows the Test Clock Input Timing Diagram
tTCKX
tTCKH TCK (Input) tTCKR VM VM tTCKR
Figure 41. Test Clock Input Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 63
Figure 42 Shows the boundary scan (JTAG) timing diagram.
TCK (Input) tBSVKH Data Inputs tTCKHOV Data Outputs tTCKHOZ Data Outputs tBSXKH
Input Data Valid
Output Data Valid
Figure 42. Boundary Scan (JTAG) Timing Figure 43 Shows the test access port timing diagram
TCK (Input) TDI TMS (Input)
tTDIVKH
tTDIXKH
Input Data Valid tTDOHOV
TDO (Output) tTDOHOZ TDO (Output)
Output Data Valid
Figure 43. Test Access Port Timing
Figure 44 Shows the TRST timing diagram.
TRST (Input) tTRST
Figure 44. TRST Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 64 Freescale Semiconductor
Hardware Design Considerations
3
3.1
3.1.1
* * *
Hardware Design Considerations
Start-up Sequencing Recommendations
Power-on Sequence
There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies. There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP, VDDRIOPLL and other MSC8144 supplies. VDDPLL should be coupled with the VDD power rail with extremely low impedance path.
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
Use the following guidelines for power-on sequencing:
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80 mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before power-up should be with slew rate less than 4V/ns. The following supplies should rise before any other supplies in any sequence * * * * * * * * VDD and VDDPLL coupled together VDDM3 VDDGE1 VDDGE2 VDDIO VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR. VDDM3IO V25M3
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 45):
I/O supplies
VDDM3, VDD, and VDDPLL
90%
Figure 45. VDDM3, VDDM3IO and V25M3 Power-on Sequence Note: 1. 2. 3. 4. 5. 6. This recommended power sequencing is different from the MSC8122/MSC8126. If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND. If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND. If the DDR interface is not used, VDDDDR and MVREF can be tied to GND. If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND. If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 65
Hardware Design Considerations
3.1.2
Start-Up Timing
Section 2.7.1 describes the start-up timing.
3.2
3.2.1
Power Supply Design Considerations
PLL Supplies
Each PLL supply must have an external RC filter for the VDDPLL input. The filter is a 10 resistor in series with two 2.2 F, low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage regulator) as long as the external RC filter is applied to each PLL separately (see Figure 46). For optimal noise filtering, place the circuit as close as possible to its VDDPLL inputs. These traces should be short and direct.
MSC8144 Voltage Regulator 10 VDDPLL0 2.2 F 2.2 F 10 VDDPLL0 2.2 F 2.2 F
10 VDDPLL0 2.2 F 2.2 F
Figure 46. PLL Supplies
3.2.2
TBD
Other Supplies
3.3
Note:
Connectivity Guidelines
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following subsections for board design and connections. The following conventions are used in describing the connectivity requirements: 1. GND indicates using a 10 k pull-down resistor (recommended) or a direct connection to the ground plane. Direct connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power consumption.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 66 Freescale Semiconductor
Hardware Design Considerations
2.
3. 4. 5. Note:
VDD indicates using a 10 k pull-up resistor (recommended) or a direct connection to the appropriate power supply. Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power consumption. Mandatory use of a pull-up or pull-down resistor it is clearly indicated as "pull-up/pull-down". NC indicates "not connected" and means do not connect anything to the pin. The phrase "in use" indicates a typical pin connection for the required function. Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of subset interface connection.
3.3.1
Note:
DDR Memory Related Pins
For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines of strobes in DDR1), please refer to Table 54.
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
3.3.1.1
DDR Interface Is Not Used
Table 54. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name Pin Connection NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144 Reference Manual for details.
MDQ[0-31] MDQS[0-3] MDQS[0-3] MA[0-15] MCK[0-2] MCK[0-2] MCS[0-1] MDM[0-3] MBA[0-2] MCAS MCKE[0-1] MODT[0-1] MDIC[0-1] MRAS MWE MECC[0-7] ECC_MDM ECC_MDQS ECC_MDQS MVREF VDDDDR Note:
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 67
Hardware Design Considerations
3.3.1.2
16-Bit DDR Memory Only
Table 55. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only
Signal Name
Table 55 lists unused pin connection when using 16-bit DDR memory. The 16 most significant data lines are not used.
Pin connection
in use pull-up to VDDDDR in use pull-down to GND in use pull-up to VDDDDR in use in use in use in use in use NC in use in use in use in use in use in use in use 1/2*VDDDDR 2.5 V or 1.8 V
MDQ[0-15] MDQ[16-31] MDQS[0-1] MDQS[2-3] MDQS[0-1] MDQS[2-3] MA[0-15] MCK[0-2] MCK[0-2] MCS[0-1] MDM[0-1] MDM[2-3] MBA[0-2] MCAS MCKE[0-1] MODT[0-1] MDIC[0-1] MRAS MWE MVREF VDDDDR
3.3.1.3
ECC Unused Pin Connections
When the error code corrected mechanism is not used in any 32- or 16-bit DDR configuration, refer to Table 56 to determine the correct pin connections. Table 56. Connectivity of Unused ECC Mechanism Pins
Signal Name MECC[0-7] ECC_MDM ECC_MDQS ECC_MDQS
Pin connection
pull-up to VDDDDR NC pull-down to GND pull-up to VDDDDR
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 68 Freescale Semiconductor
Hardware Design Considerations
3.3.2
3.3.2.1
Serial RapidIO Interface Related Pins
Serial RapidIO interface Is Not Used
Table 57. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used
Signal Name SRIO_IMP_CAL_RX SRIO_IMP_CAL_TX SRIO_REF_CLK SRIO_REF_CLK SRIO_RXD[0-3] SRIO_RXD[0-3] SRIO_TXD[0-3] SRIO_TXD[0-3] VDDRIOPLL GNDRIOPLL GNDSXP GNDSXC VDDSXP VDDSXC Pin Connection GND GND GND GND GND GND NC NC GND GND GND GND GND GND
3.3.2.2
Serial RapidIO Specific Lane Is Not Used
Table 58. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used
Signal Name Pin Connection in use in use in use in use GNDSXC GNDSXC NC NC in use in use GNDSXP GNDSXC 1.0 V 1.0 V The x indicates the lane number {0,1,2,3} for all unused lanes.
SRIO_IMP_CAL_RX SRIO_IMP_CAL_TX SRIO_REF_CLK SRIO_REF_CLK SRIO_RXDx SRIO_RXDx SRIO_TXDx SRIO_TXDx VDDRIOPLL GNDRIOPLL GNDSXP GNDSXC VDDSXP VDDSXC Note:
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 69
Hardware Design Considerations
3.3.3
M3 Memory Related Pins
Table 59. Connectivity of M3 Related Pins When M3 Memory Is Not Used
Signal Name Pin Connection NC GND GND GND
M3_RESET V25M3 VDDM3 VDDM3IO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 70 Freescale Semiconductor
Hardware Design Considerations
3.3.4
3.3.4.1
Note:
Ethernet Related Pins
Ethernet Controller 1 (GE1) Related Pins
Table 60 and Table 61 assume that the alternate function of the specified pin is not used. If the alternate function is used, connect the pin as required to support that function.
3.3.4.1.1
GE1 Interface Is Not Used
Table 60 assumes that the GE1 signals are not used for any purpose (including any multiplexed functions) and that VDDGE1 is tied to GND. Table 60. Connectivity of GE1 Related Pins When the GE1 Interface Is Not Used
Signal Name GE1_COL GE1_CRS GE1_RD[0-4] GE1_RX_ER GE1_RX_CLK GE1_RX_DV GE1_SGMII_RX GE1_SGMII_RX GE1_SGMII_TX GE1_SGMII_TX GE1_TD[0-4] GE1_TX_CLK GE1_TX_EN GE1_TX_ER Pin Connection NC NC NC NC NC NC GNDSXC GNDSXC NC NC NC NC NC NC
3.3.4.1.2
Subset of GE1 Pins Required
When only a subset of the whole GE1 interface is used, such as for RMII, the unused GE1 pins should be connected as described in Table 61. This table assumes that the unused GE1 pins are not used for any purpose (including any multiplexed function) and that VDDGE1 is tied to either 2.5 V or 3.3 V. Table 61. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required
Signal Name GE1_COL GE1_CRS GE1_RD[0-3] GE1_RX_ER GE1_RX_CLK GE1_RX_DV GE1_SGMII_RX GE1_SGMII_RX GE1_SGMII_TX Pin Connection GND GND GND GND GND GND GNDSXC GNDSXC NC
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 71
Hardware Design Considerations
Table 61. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)
Signal Name GE1_SGMII_TX GE1_TD[0-3] GE1_TX_CLK GE1_TX_EN GE1_TX_ER Pin Connection NC NC GND NC NC
3.3.4.2
Note:
Ethernet Controller 2 (GE2) Related Pins
Table 62 and Table 64 assume that the alternate function of the specified pin is not used. If the alternate function is used, connect the pin as required to support that function.
3.3.4.2.1
GE2 interface Is Not Used
Table 62 assumes that the GE2 pins are not used for any purpose (including any multiplexed function) and that VDDGE2 is tied to GND. Table 62. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used
Signal Name GE2_RD[0-3] GE2_RX_CLK GE2_RX_DV GE2_RX_ER GE2_SGMII_RX GE2_SGMII_RX GE2_SGMII_TX GE2_SGMII_TX GE2_TCK GE2_TD[0-3] GE2_TX_EN Pin Connection NC NC NC NC GNDSXC GNDSXC NC NC Nc Nc NC
3.3.4.2.2
Subset of GE2 Pins Required
When only a subset of the whole GE2 interface is used, such as for RMII, the unused GE2 pins should be connected as described in Table 63. The table assumes that the unused GE2 pins are not used for any purpose (including any multiplexed functions) and that VDDGE2 is tied to either 2.5 V or 3.3 B. Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required
Signal Name GE2_RD[0-3] GE2_RX_CLK GE2_RX_DV GE2_RX_ER GE2_SGMII_RX Pin Connection GND GND GND GND GNDSXC
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 72 Freescale Semiconductor
Hardware Design Considerations
Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)
Signal Name GE2_SGMII_RX GE2_SGMII_TX GE2_SGMII_TX GE2_TCK GE2_TD[0-3] GE2_TX_EN Pin Connection GNDSXC NC NC NC NC NC
3.3.4.3
GE1 and GE2 Management Pins
GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that is, VDDGE2 is connected to GND), Table 64 lists the recommended management pin connections. Table 64. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used
Signal Name GE_MDC GE_MDIO Pin Connection NC NC
3.3.5
UTOPIA Related Pins
Table 65 lists the board connections of the UTOPIA pins when the entire UTOPIA interface is not used or subset of UTOPIA interface is used. For multiplexing options that select a subset of the UTOPIA interface, use the connections described in Table 65 for those signals that are not selected. Table 65 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 65. Connectivity of UTOPIA Related Pins When UTOPIA Interface Is Not Used
Signal Name UTP_IR UTP_RADDR[0-4] UTP_RCLAV_PDRPA UTP_RCLK UTP_RD[0-15] UTP_REN UTP_RPRTY UTP_RSOC UTP_TADDR[0-4] UTP_TCLAV UTP_TCLK UTP_TD[0-15] UTP_TEN UTP_TPRTY UTP_TSOC VDDIO Pin Connection GND VDDIO NC GND GND VDDIO GND GND VDDIO NC GND NC VDDIO NC NC 3.3 V
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 73
Hardware Design Considerations
3.3.6
TDM Interface Related Pins
Table 66 lists the board connections of the TDM pins when an entire specific TDM is not used. For multiplexing options that select a subset of a TDM interface, use the connections described in Table 66 for those signals that are not selected. Table 66 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 66. Connectivity of TDM Related Pins When TDM Interface Is Not Used
Signal Name TDMxRCLK TDMxRDAT TDMxRSYN TDMxTCLK TDMTxDAT TDMxTSYN VDDIO Notes: 1. 2. Pin Connection GND GND GND GND GND GND 3.3 V x = {0, 1, 2,3, 4, 5, 6, 7} In case of subset of TDM interface usage please make sure to disable unused TDM modules. See Chapter 20, TDM, in the MSC8144 Reference Manual for details.
3.3.7
PCI Related Pins
Table 67 lists the board connections of the pins when PCI is not used. Table 67 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 67. Connectivity of PCI Related Pins When PCI Is Not Used
Signal Name PCI_AD[0-31] PCI_CBE[0-3] PCI_CLK_IN PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDS PCI_IRDY PCI_PAR PCI_PERR PCI_REQ PCI_SERR PCI_STOP PCI_TRDY VDDIO Pin Connection GND GND GND VDDIO VDDIO VDDIO GND VDDIO GND VDDIO NC VDDIO VDDIO VDDIO 3.3 V
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 74 Freescale Semiconductor
Hardware Design Considerations
3.3.8
Miscellaneous Pins
Table 68 lists the board connections for the pins if they are required by the system design. Table 68 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 68. Connectivity of Individual Pins When They Are Not Required
Signal Name CLKOUT EE0 EE1 GPIO[0-31] SCL SDA INT_OUT IRQ[0-15] NMI NMI_OUT RC[0-16] RC_LDF STOP_BS TCK TDI TDO TMR[0-4] TMS TRST URXD UTXD VDDIO Note: Pin Connection NC GND NC NC See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. NC See the GPIO connectivity guidelines in this table. VDDIO NC GND NC GND GND GND NC See the GPIO connectivity guidelines in this table. GND GND See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. 3.3 V When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.
Note:
For details on configuration, see the MSC8144 Reference Manual. For additional information, refer to the MSC8144 Design Checklist (AN3202).
3.4
TBD
External DDR SDRAM Selection
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 75
Ordering Information
3.5
Thermal Considerations
TJ = TA + (RJA x PD) Equation 1
An estimation of the chip-junction temperature, TJ, in C can be obtained from the following:
where
TA = ambient temperature near the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD x VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8144 are listed in Table 5. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8144 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ:
TJ = TT + (JA x PD) Equation 2
where TT = thermocouple (or infrared) temperature on top of the package (C) JA = thermal characterization parameter (C/W) PD = power dissipation in the package (W)
4
Ordering Information
Core Frequency (MHz)
800 1000
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part
MSC8144
Package Type
Flip Chip Plastic Ball Grid Array (FC-PBGA)
Spheres
Lead-free
Core Voltage
1.0 V
Operating Temperature
-40 to 105C 0 to 90C
Order Number
TBD TBD
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 76 Freescale Semiconductor
Package Information
5
Package Information
Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement should exclude any effect of marking. 6. Capacitors may not be present on all devices. 7. Caution must be taken not to short exposed metal capacitor pads on package top.
CASE NO. 1842-02
Figure 47. MSC8144 Mechanical Information, 783-ball FC-PBGA Package
6
* * * * *
Product Documentation
MSC8144 Technical Data Sheet (MSC8144). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8144 device. MSC8144 Reference Manual (MSC8144RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144 device. SC3400 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set. MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and registers.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 77
Revision History
7
Revision History
Table 69. Document Revision History
Table 69 provides a revision history for this data sheet.
Revision 0 1 Date Feb. 2007 Apr. 2007 * Initial public release. * * * * * * * * * * Adds new I/O multiplexing mode 7 that supports POS functionality. Updates reference voltage supply for pins G5, H7, and H8 in Table 1. Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1. Adds input clock duty cycles in Table 20. Updates PCI AC timings in Table 38. Removes UTOPIA internal clock specifications in Table 49. Updates JTAG timings in Table 53. Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4. Miscellaneous pin connectivity guidelines were updated in Table 68. Updates name of core subsystem reference manual. Description
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 78 Freescale Semiconductor
Revision History
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 79
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Document Number: MSC8144
Rev. 1 5/2007

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